1. Field of the Invention
The present invention relates to telecommunications apparatus and is particularly concerned with broadband signal space switching apparatus.
2. Description of the Prior Art
Recent developments in telecommunications technology have led to service-integrated communications transmission/ systems for narrow band and broadband communication services which provide light waveguides as transmission media in the region of the subscriber lines, both the narrow band communication services such as, in particular, 64 Kbit/s digital telephony, and broadband communication services such as, particularly, 140 Mbit/s picture telephony, being conducted via the light waveguides, whereby, however, dedicated narrow band signal switching devices and broadband signal switching devices (preferably having shared control devices) are provided in the switching centers. In this context, reference is taken to the German Pat. No. 24 21 002, fully incorporated herein by this reference.
It is known in the context of a broadband signal time-division multiplex switching device, whose crosspoints are respectively utilized in time-division multiplex for a plurality of connections, to connect respectively two lines with the assistance of a gate which is switched on and off by a crosspoint-associated memory cell constructed as a D flip-flop circuit, whereby the crosspoint-associated memory cell, whose clock input is supplied with an appropriate timing signal, is selected in only one coordinate direction, namely at its D input. In this connection, reference should be taken to Pfannschmidt, "Arbeitsgeschwindigkeitsgrenzen von Koppelnetzwerken fur Breitband-Digitalsignale", Dissertation, Braunschweig 1978, FIG. 6.7, with further reference to FIG. 6.4. In view of a time-division multiplex factor of about 4-8 obtainable with a bit rate of 140 Mbit/s and of the involved circuit technology thereby required, however, exclusive space switching devices are currently preferred for switching the connections through-connected via the individual crosspoints being separated from one another only in a spatial manner.
An exclusive broadband signal space switching matrix network can be constructed as a crosspoint matrix in complementary-metal-oxide-semiconductor (CMOS) technology provided with input amplifiers and output amplifiers in whose crosspoints the switching elements are respectively controlled by a decoder-controlled, crosspoint-associated holding memory cell, whereby the switching elements are respectively constructed as CMOS transfer gates (CMOS transmission gates) of the type disclosed in ISS'84 Conference Papers 23C1, FIG. 9). Proceeding by way of a row-associated and a column-associated selection line, the crosspoint-associated holding memory cells of an exclusive space switching matrix can be respectively selected in two coordinates as disclosed in the aforementioned Pfannschmidt publication with respect to FIG. 6.4.
In a broadband signal space switching device comprising switching elements constructed in field effect transistor (FET technology, which are respectively formed with a CMOS inverter circuit comprising MOS transistors of the enhancement type, which has its input side connected to the appertaining signal input line and its output side leading to the appertaining signal output line, whereby a p-channel depletion transistor having its control electrode connected to the output of the memory cell is connected between the p-channel enhancement transistor thereof and the appertaining feed potential source and an n-channel depletion channel transistor having its control electrode connected to the complementary output of the memory cell is inserted between the n-channel enhancement transistor and the appertaining feed potential source, these switching elements can be respectively controlled by a cross-point-associated memory cell formed with an n-channel transistor and two feedback inverters, as discussed in the publication ISS'84 Conference Papers 31C3, with respect to FIG. 14.
In a broadband space switching device comprising a crosspoint matrix constructed in FET technology, the switching elements can also be respectively formed with an n-channel transistor having its drain-source path lying between a matrix input line and a matrix output line (cf. ISS'84 Conference Papers 31C3, with respect to FIG. 12), these switching elements being respectively controlled by a cross-point associated memory cell having two cross-coupled inverter circuits and which is controlled in two coordinates by two drive decoders, the one being connected at the input side to the appertaining, inverting decoder output of the one drive decoder via a first n-channel transistor and the other being connected at the input side to the appertaining non-inverting decoder output of the same drive decoder via a second n-channel transistor, whereby both n-channel transistors in turn, have their control electrodes charged with the output signal of the appertaining decoder output of the other drive selection decoder. In this connection, one may take reference to the publications Rev. ECL 25 (1977) 1-2, 43 . . . 51, FIG. 1, IEEE Journal of Solid State Circuits 9 (1974) 3, 142 . . . 147, FIG. 1, and Electronics and Communications in Japan, 53-A (1970) 10, 54 . . . 62, FIG. 5, and the European Patent Application No. EP-A-0 073 920, FIG. 5.